Method for designing cascaded multi-level inverter with minimized large-scale voltage distortion

ABSTRACT

A method for designing cascaded multi-level inverters with minimization of large-scale voltage distortion, based on KKT (Karush-Kuhn-Tucker) conditions and with simplified computation of conduction angles, simplifies the computation process, and is conducive to on-line calculation. Meanwhile, its fundamental voltage is adaptive, minimization of total harmonic is realized for cascaded multi-level inverters at high-voltage, and voltage power quality at grid connected nodes is improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

The subject application claims priority on Chinese Patent ApplicationNo. CN201410245719.1 filed on Jun. 5, 2014. The contents and subjectmatter of the Chinese priority application are incorporated herein byreference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to electric and electronic technology, andin particular, relates to a method for designing a cascaded multi-levelinverter with minimized large-scale voltage distortion.

BACKGROUND OF THE INVENTION

Inverters are used more and more with the development of the electricand electronic technology. Cascaded inverters based on pulse widthmodulation (PWM) are popular in medium and high power level systems.Cascaded inverters are modulated in high or low frequency according tothe switching frequency. Regular high frequency modulation featuressinusoidal pulse width modulation (SPWN), selected harmonic eliminationPWM (SHEPWM), space vector pulse width modulation (SVPWM), etc. Comparedwith the high frequency modulation, the low frequency modulation reducesswitching loss and switching stress of a device, lengthens itslife-time, and increases system efficiency.

In a step modulation, computation of conductance angles of variousinverter levels is a research hotspot. Methods for computing conductanceangles include: selected harmonic elimination (SHE), equal-area method,minimum area-difference method, and minimum total harmonic distortion(THD). The SHE method aims to eliminate low-order harmonic in a voltageoutput waveform, but its computation is complicated as a set ofmultivariate nonlinear transcendental equations need to be solved. Theequal-area method requires that, at each specific time interval, thesinusoidal reference voltage equals the integral of the step modulatedwave, but it lacks the optimization of the harmonic distortion, andhence the distortion of the amplitude of the voltage base frequencybecomes possible. The minimum area-difference method aims at minimizingthe integral of the difference between the sinusoidal reference voltageand the step voltage, which again may result in the distortion of theamplitude of the voltage base frequency.

Integration of a large number of inverters brings possible harmonicissues to the system. Total harmonic distortion is an importantparameter for assessing the quality of the output waveform of theinverter, therefore, the investigation of the cascaded multi-levelinverters with minimization of distortion is an urgent task. However,the cascaded inverters in the existing technology have big distortionand affect power quality at the nodes of integration.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method for designingcascaded multi-level inverters with minimized large-scale voltagedistortion. The method of the present invention is based on KKT(Karush-Kuhn-Tucker) conditions; it simplifies the computation forconduction angles and the computation process, and is friendly toon-line calculation. Meanwhile, its fundamental voltage is adaptive,minimization of total harmonic is realized for cascaded multi-levelinverters at high-voltage, and voltage power quality at grid connectednodes is improved.

The technical solution of the present invention is as follows:

A method for designing cascaded multi-level inverters with minimizationof large-scale voltage distortion, the design method of the presentinvention comprises the following steps: determining N as a number ofinverter modules and DC voltage sources in a cascaded multi-levelinverter based on a maximum inverter level of the cascaded multi-levelinverter H, a step series S, and an inverter level j; applying Ninverter modules and DC voltage sources in the cascaded multi-levelinverter; connecting a positive electrode of a DC bus of each of theinverter modules with a positive electrode of a corresponding DC voltagesource; connecting a negative electrode of the DC bus of each of theinverter modules with a negative electrode of the corresponding DCvoltage source; connecting an input control terminal for a conductionangle of the inverter module with a corresponding output controlterminal of a controller; connecting an AC output terminal of theinverter module with an AC voltage input terminal corresponding to thecontroller; and connecting the AC voltage input terminal of thecontroller with the AC output terminal of the corresponding invertermodule. The number of inverter modules and DC voltage sources in thecascaded multi-level inverter, N, is determined by

1) computing lower boundary points M_(min) (S) of a modulationcoefficient m according to the equation

${M_{\min}(S)} = {\frac{4}{\pi}{\sum\limits_{j = 1}^{S}\;\sqrt{1 - ( \frac{{2\; j} - 1}{{2\; S} - 1} )^{2}}}}$

 under the condition of λ≧2S−1 where S is a step series, S=1, 2, . . . ,H, H is a maximum inverter level of the cascaded multi-level inverter,and j is an inverter level;

2) selecting a step series S₀, wherein the modulation coefficient mfulfills m∈(M_(min)(S₀),M_(min)(S₀+1)], when the modulation coefficientm falls into an interval (0,M_(min)(H+1)], S₀ satisfies

${{\sum\limits_{j = 1}^{S_{0}}\;\sqrt{1 - ( \frac{{2\; j} - 1}{\lambda} )^{2}}} = {\frac{\pi}{4}m}};$

 and when m falls into an interval

$( {{M_{\min}( {H + 1} )},\frac{4\; H}{\pi}} \rbrack,$

 S₀ is selected so that S₀=H with j being the inverter level, j=0, 1, 2,. . . , H, and λ being a parameter;

3) computing λ according to the formula

${{\sum\limits_{j = 1}^{S_{0}}\;\sqrt{1 - ( \frac{{2\; j} - 1}{\lambda} )^{2}}} = {\frac{\pi}{4}m}};$

4) computing a sinusoidal value for each conductance angle θ_(j)according to the formula

${{\sin\;\theta_{j}^{*}} = \frac{{2\; j} - 1}{\lambda}},{j \in {\overset{\_}{J}( \theta^{*} )}},$

 where j=1, 2, . . . , H, and the sinusoidal value is set to be 1 if itexceeds 1;

5) determining the conductance angle θ_(j), j=1, 2, . . . , H for eachthe inverter level via an inverse trigonometric function;

6) determining the number N of the inverter module and of the DC voltagesource according to the equation H=2^(N)−1.

Further, the present invention provides a cascaded multi-level inverterthat is designed by the method of the present invention. The cascadedmulti-level inverter comprises inverter modules, a number of theinverter modules being N, each of the inverter modules having 4full-control switching devices, an H bridge having anti-parallel diodes,a control terminal for a conduction angle of the inverter module, an ACoutput terminal, and a DC bus, and the DC bus having a positiveelectrode and a negative electrode; direct-current (DC) voltage sources,a number of the direct-current voltage sources being N, and each of theDC voltage sources having a positive electrode and a negative electrode;and a controller having a control terminal for output conducting signalsand an AC voltage input terminal. The positive electrode of the DC busof each of the inverter modules is connected with the positive electrodeof a corresponding DC voltage source; the negative electrode of the DCbus of each of the inverter modules is connected with the negativeelectrode of the corresponding DC voltage source; the input controlterminal for the conduction angle of the inverter module is connectedwith the corresponding output control terminal of the controller; the ACoutput terminal of the inverter module is connected with the AC voltageinput terminal corresponding to the controller;

Compared with the prior art, the present invention features thefollowing:

1. The design method of cascaded multi-level inverter for minimizationof large-scale voltage distortion of the present invention is a stepmodulation algorithm based on Karush-Kuhn-Tucker (KKT) conditions. Itgives a method of computation for the corresponding conductance anglesvia strict mathematical deductions, and thus obtains an analyticalexpression of the total harmonic. The proposed step modulation strategymay minimize total harmonic distortion under any modulation coefficient.It has strict mathematical deductions and simple algorithm; it isadaptive to a large range of voltage, and provides a scientificfoundation for online computation of conductance angles and forcontrolling of total harmonic of cascaded multi-level inverters. Theproposed cascaded multi-level inverter for minimization of large-scalevoltage distortion is characterized in small harmonic in a large rangeof fundamental voltage.

2. The computation is highly convenient, which significantly reducescomputational work.

3. It is adaptable to a wide range of fundamental voltage.

4. It improves power quality at grid connected nodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of the cascaded multi-level inverter forminimization of large-scale voltage distortion of the present invention.

FIG. 2 is a procedure of the computation method of the presentinvention.

FIG. 3 shows the output voltage and harmonic components at variousorders with modulation coefficient m=5.

FIG. 4 shows the output voltage and harmonic components at variousorders with modulation coefficient m=15.

FIG. 5 shows a curve of distortion of total harmonic varying withmodulation coefficient.

DETAILED DESCRIPTION OF THE INVENTION AND EMBODIMENTS

With references to drawings and embodiments hereinafter provided in anon-limiting way, the present invention will be further explained.

The underlying principle of the present invention is described below.

The voltage total harmonic distortion (THD) of the cascaded multi-levelinverter for minimization of large-scale voltage distortion according tothe present invention is expressed by formula (1) to be shown below. Theproblem we are facing is: with a specific modulation coefficient m andunder the condition of minimum total harmonic distortion, a set ofconductance angles θ_(k), k=1, 2, . . . , 2^(N)−1 are to be obtained.

$\begin{matrix}\begin{matrix}{{T\; H\; D} = \sqrt{\frac{\sum\limits_{n = 3}^{+ \infty}\; U_{n}^{2}}{U_{1}^{2}}}} \\{= \sqrt{\frac{{\sum\limits_{n = 1}^{+ \infty}\; U_{n}^{2}} - U_{1}^{2}}{U_{1}^{2}}}} \\{= \sqrt{{\frac{2}{m^{2}}\lbrack {F^{2} - {\frac{2}{\pi}{\sum\limits_{k = 1}^{F}\;{( {{2\; k} - 1} )\theta_{k}}}}} \rbrack} - 1}}\end{matrix} & (1)\end{matrix}$

 where m is the modulation coefficient, U_(n) is the component of then^(th) harmonic, F stands for the maximum number of inverter levels inthe positive half cycle, θ_(k) signifies the conductance angle of theoutput voltage step-jumping from (k−1)V_(bs) to kV_(bs), and V_(bs)represents the voltage value of the minimum DC voltage source.

Let V_(bs)=1, and the maximum number of the inverter levels of thecascaded multi-level inverter H=2^(N)−1. The equivalent of theaforementioned problem is the following optimization problem:

$\begin{matrix}{{\min\;{f(\theta)}} = {- {\sum\limits_{k = 1}^{H}\;{( {{2\; k} - 1} )\theta_{k}}}}} & (2) \\{{{subject}\mspace{14mu}{to}\mspace{14mu}{h(\theta)}} = {{{m\frac{\pi}{4}} - {\sum\limits_{k = 1}^{H}\;\lbrack {\cos( \theta_{k} )} \rbrack}} = 0}} & (3) \\{{g_{0}(\theta)} = {{- \theta_{1}} \leq 0}} & (4) \\{{{g_{j}(\theta)} = {{\theta_{j} - \theta_{j + 1}} \leq 0}},{j = 1},2,\ldots\mspace{14mu},{H - 1}} & (5) \\{{g_{H}(\theta)} = {{\theta_{H} - \frac{\pi}{2}} \leq 0}} & (6)\end{matrix}$

 where θ=[θ₁, θ₂ . . . θ_(H)]^(T), ƒ(θ), g(θ) and h(θ) are allcontinuous derivable functions with respect to θ;

Let θ* be a local extreme point of ƒ(θ), then there exists a λ andμ_(j)≧0(j=0, 1, 2, . . . , H) satisfying:

$\begin{matrix}{{{\nabla{f( \theta^{*} )}} + {\lambda{\nabla\;{h( \theta^{*} )}}} + {\sum\limits_{j = 0}^{H}\;{\mu_{j}{\nabla{g_{j}( \theta^{*} )}}}}} = 0} & (7) \\{{{\mu_{j}{g_{j}( \theta^{*} )}} = 0},{{j \in J} = \{ {0,1,\ldots\mspace{14mu},H} \}}} & (8)\end{matrix}$

 For a specific solution θ*, define effective subsetj(θ*)={j∈J,g_(j)(θ*)=0}.

It follows from formula (7) that:−(2j−1)+λ sin θ*_(j)−μ_(j−1)+μ_(j)=0  (9)where θ₁, θ₂, . . . , θ_(S) are all non-zeros and different from oneanother. For any j>S, j∈J(θ*) and g_(j)(θ*)=0, we have

${\theta_{S + 1}^{*} = {\theta_{S + 2}^{*} = {\ldots = {\theta_{H}^{*} = \frac{\pi}{2}}}}},$S being a step series.Consider the non-effective subset J(θ*)={j≦S or j∉J(θ*)}, it followsfrom formula (5) that:

$\begin{matrix}{{{\sin\;\theta_{j}^{*}} = \frac{{2\; j} - 1}{\lambda}},{j \in {\overset{\_}{J}( \theta^{*} )}}} & (10)\end{matrix}$

Under the constraint of h(θ), it follows that

$\begin{matrix}{{\sum\limits_{j = 1}^{S}\;\sqrt{1 - ( \frac{{2\; j} - 1}{\lambda} )^{2}}} = {\frac{\pi}{4}m}} & (11)\end{matrix}$

The above formula (10) thus constitutes the basis for designing theconductance angles that minimize the total harmonic of the controller ofthe cascaded multi-level inverter according to the present invention.

Refer to FIG. 1, it is a single-phase schematic diagram of a cascadedmulti-level inverter for minimization of large-scale voltage distortionaccording to the present invention, illustrating a three-phase casecomprising three single phases. FIG. 2 shows the procedure for thecomputation of conductance angles of the controller of the cascadedmulti-level inverter for minimization of large-scale voltage distortion.

The computation method is implemented as follows:

For a specific S, there exists a corresponding modulation coefficientinterval M(S) such that equations (10) and (11) are fulfilled. Its lowerbound is set as M_(min), and its upper bound as M_(max)(S). For the leftside of equation (11) to be a real number, λ≧2S−1 must be satisfied.Accordingly the lower bound of M(S) is

$\begin{matrix}{{M_{\min}(S)} = {\frac{4}{\pi}{\sum\limits_{j = 1}^{S}\;\sqrt{1 - ( \frac{{2\; j} - 1}{{2\; S} - 1} )^{2}}}}} & (12)\end{matrix}$

When M(S) is maximized, λ→+∞. That is,

$\begin{matrix}{{M_{\max}(S)} = {\frac{4}{\pi}S}} & (13)\end{matrix}$

When Δ=2S−1,

${\theta_{S}^{*} = \frac{\pi}{2}},$

 it is obvious that

${\theta_{S + 1}^{*} = \frac{\pi}{2}},$

 and then g_(S)(θ*)=0, S∈J(θ*), which contradicts the above assumption.M(S) therefore cannot completely reach its lower bound. While λ→+∞, cosθ*₁=cos θ*₂= . . . =cos θ*_(S)=1, contradicting the fact that θ₁, θ₂, .. . , θ_(S) are non-zeros. M(S) therefore does not contain its upperbound. Hence, the modulation coefficient interval corresponding to S isM(S)=(M_(min) (S), M_(max)(S)). When N=4, H=2^(N)−1=15, M_(min)(S) andM_(max)(S) corresponding to each level of S are shown in Table 1.

TABLE 1 M_(min) (S) and M_(max) (S) S M_(min) (S) M_(max) (S) 1 0 1.27322 1.2004 2.5465 3 2.2661 3.8197 4 3.3016 5.0930 5 4.3247 6.3662 6 5.34137.6394 7 6.3539 8.9127 8 7.3639 10.1859 9 8.3721 11.4592 10 9.378912.7324 11 10.3848 14.0056 12 11.3899 15.2789 13 12.3944 16.5521 1413.3984 17.8254 15 14.4019 19.0986 16 15.4051 20.3718

For a specific modulation coefficient m, any S′ satisfying m∈M(S′) is asuitable selection of step series. We may obtain every S′ that satisfiesm∈M(S′), and obtain a λ corresponding to m and S′ via equation (12), andobtain a set of local optimal solutions {θ*} by substituting λ into(10). This set of local optimal solutions are the candidates for theglobal optimal solution.

The specific steps for computing conductance angles for minimization oftotal harmonic distortion are as follows:

1) Computing division points M_(min)(S) according to equation (12),wherein S=1, 2, . . . , H.

2) Selecting a suitable step series S₀, wherein the modulationcoefficient m∈(M_(min)(S₀),M_(min)(S₀+1)].

3) Computing λ according to equation (11).

4) Computing sinusoidal values for various conductance angles accordingto equation (10), and let it be 1 if it exceeds 1.

5) Computing conductance angles θ_(k), k=1, 2, . . . , H for variousinverter levels via inverse trigonometric functions.

It should be pointed out that the above algorithm holds only when themodulation coefficient falls into the interval (0,M_(min)(H+1)]. Whenthe coefficient is in the interval

$( {{M_{\min}( {H + 1} )},\frac{4\; H}{\pi}} \rbrack,$

 the solution can only proceed by selecting S=H. We define this intervalas the over modulation interval for the step modulation.

With the analytical computing formula (10), harmonic components ofvarious orders for the output voltage of a cascaded multi-level invertercorresponding to a modulation coefficient can be computed. FIG. 3 showsthe output voltage with its harmonic components at various orders withmodulation coefficient m=5. FIG. 4 shows the output voltage with itsharmonic components at various orders with modulation coefficient m=15.FIG. 5 shows a curve of distortion of total harmonic of the outputvoltage of a cascaded multi-level inverter varying with modulationcoefficient. Accordingly, the present invention discloses a simple andaccurate analytical formula for computing output voltage THD of acascaded multi-level inverter, suitable for online computation ofconductance angles.

We claim:
 1. A method of designing a cascaded multi-level inverter forminimized large-scale voltage distortion, comprising: determining N as anumber of inverter modules and DC voltage sources in a cascadedmulti-level inverter based on a maximum inverter level of the cascadedmulti-level inverter H, a step series S, and an inverter level j;applying N inverter modules and DC voltage sources in the cascadedmulti-level inverter; connecting a positive electrode of a DC bus ofeach of the inverter modules with a positive electrode of acorresponding DC voltage source; connecting a negative electrode of theDC bus of each of the inverter modules with a negative electrode of thecorresponding DC voltage source; connecting an input control terminalfor a conduction angle of the inverter module with a correspondingoutput control terminal of a controller; connecting an AC outputterminal of the inverter module with an AC voltage input terminalcorresponding to the controller; and connecting the AC voltage inputterminal of the controller with the AC output terminal of thecorresponding inverter module, wherein N is determined by computinglower boundary points M_(min)(S) of a modulation coefficient m accordingto an equation${M_{\min}(S)} = {\frac{4}{\pi}{\sum\limits_{j = 1}^{S}\;\sqrt{1 - ( \frac{{2\; j} - 1}{{2\; S} - 1} )^{2}}}}$ under a condition of λ≧2S−1, wherein S is the step series and S=1, 2, .. . , H, H is the maximum inverter level of a cascaded multi-levelinverter, and j is the inverter level; selecting a step series S₀,wherein the modulation coefficient m fulfillsm∈(M_(min)(S₀),M_(min)(S₀+1)], when the modulation coefficient m fallsinto an interval (0,M_(min)(H+1)], S₀ satisfies${{\sum\limits_{j = 1}^{S_{0}}\;\sqrt{1 - ( \frac{{2\; j} - 1}{\lambda} )^{2}}} = {\frac{\pi}{4}m}},$ and when m falls into an interval$( {{M_{\min}( {H + 1} )},\frac{4\; H}{\pi}} \rbrack,$ S₀ is selected so that S₀=H, with j being the inverter level, j=0, 1,2, . . . , H, and λ being a parameter; computing λ according to theformula${{\sum\limits_{j = 1}^{S_{0}}\;\sqrt{1 - ( \frac{{2\; j} - 1}{\lambda} )^{2}}} = {\frac{\pi}{4}m}};$computing a sinusoidal value for each conductance angle θ_(j) accordingto a formula${{\sin\;\theta_{j}^{*}} = \frac{{2\; j} - 1}{\lambda}},{j \in {\overset{\_}{J}( \theta^{*} )}},$ where j=1,2, . . . ,H, and the sinusoidal value is set to be 1 if itexceeds 1; determining the conductance angle θ_(j), j=1,2, . . . ,H foreach of the inverter levels via an inverse trigonometric function; anddetermining N according to an equation H=2^(N)−1.
 2. A cascadedmulti-level inverter designed by the method as described in claim 1,comprising: inverter modules, a number of the inverter modules being N,each of the inverter modules having 4 full-control switching devices, anH bridge having anti-parallel diodes, a control terminal for aconduction angle of the inverter module, an AC output terminal, and a DCbus, and the DC bus having a positive electrode and a negativeelectrode, direct-current (DC) voltage sources, a number of thedirect-current voltage sources being N, and each of the DC voltagesources having a positive electrode and a negative electrode, and acontroller having a control terminal for output conductance signals andan AC voltage input terminal, wherein the positive electrode of the DCbus of each of the inverter modules is connected with the positiveelectrode of a corresponding DC voltage source; the negative electrodeof the DC bus of each of the inverter modules is connected with thenegative electrode of the corresponding DC voltage source; the inputcontrol terminal for the conduction angle of the inverter module isconnected with the corresponding output control terminal of thecontroller; the AC output terminal of the inverter module is connectedwith the AC voltage input terminal corresponding to the controller; andthe AC voltage input terminal of the controller is connected with the ACoutput terminal of the corresponding inverter module.